The present disclosure relates generally to semiconductor manufacturing and, in particular, to a method of selecting mask patterns used in semiconductor device manufacturing resolution enhancement techniques; in particular for optical proximity correction (OPC) and resist model calibration.
When developing a process to manufacture chips at a new technology node or resolution scale, a number of preprocessing steps are developed to guarantee yield of the scaled down device features. One of these steps is the optical proximity correction (OPC) tool which is part of resolution enhancement techniques (RET) used to shape the mask for better yield. To calibrate and verify OPC's optical and resist models, one or more patterns are selected that produce features of the integrated chip within selected specifications. For each new OPC version, design of the mask begins from scratch. Typically, the patterns are pulled from a library of patterns and a modeler enters into a process of selecting those patterns that are to be used in the mask. The set of patterns pulled from the library and used in the mask are called sample plan (SP). The final set of patterns used in the OPC models calibration and verification are further selected based on their respective wafer image quality criteria. Several sub-processes of this process are currently performed manually, and are therefore slow to complete. Typical time frames for completing the entire selection process may take weeks.